An integrated circuit consists of electronic devices electrically coupled by conductive trace elements called interconnect lines (interconnects). Interconnects are patterned from layers of electrically conductive materials (e.g., aluminum, doped polysilicon, etc.) formed on the surface of a silicon wafer. Multiple layers (or levels) of closely-spaced interconnects allow an increase in the density of devices formed on semiconductor wafers. Electrical separation of stacked interconnect layers is achieved by placing an electrically insulating material (i.e., interlevel dielectric layer) between the vertically spaced interconnect layers.
In very large scale integrated (VLSI) circuit devices, several wiring layers are often required to connect together the active and/or passive elements in a VLSI semiconductor chip. The interconnection structure typically consists of thin conductive lines separated by insulation in one layer or level and connected through vias or studs from contacts of the elements of the semiconductor chip or to a similar layer in another level of interconnections. With the trend to higher and higher levels of integration in semiconductor devices to ultra large scale integrated (ULSI) circuits, the space or gap between the wires or conductive lines to be filled with insulation is becoming extremely narrow between some of the conductive lines, such as about 0.5 microns and smaller. In addition, when the height of the conductive lines is increased, it is more difficult to fill gaps between the lines, especially when the aspect ratio is 2 to 1 or greater with a gap distance of 0.5 microns or smaller.
In order to satisfy increasingly higher density requirements, the dimensions of integrated circuits are continuously reduced and, hence, the line widths of the conductors decreased into the submicron range. While the conductors become narrower and narrower, the stresses imposed upon the conductive material increase, thereby resulting in a high failure rate. Many of these failures stem from defects or voids generated by stress migration as a result of thermal stresses caused by exposure at different temperatures or to subsequent processing. Other types of voids are generated by electromigration and during various production steps, such as etching. These voids, which can range from 0.1 microns to about 10 microns or more, ultimately lead to failures in narrow electrical lines by causing open circuits.
Interconnects are typically made of a metal stack structure. Multilayer interconnect structures can be made of two, three, and even four or more layers of metal or metal alloys. After formation of the stacked interconnect structures and appropriate patterning, an interlayer dielectric (ILD) is deposited. A conventional three layer stacked interconnect structure is shown in FIGS. 1A and 1B. Referring to FIG. 1B, stacked interconnect structure 12 is situated on a substrate 10, both of which are covered by an ILD material 14. The ILD serves to electrically separate stacked interconnect layers and structures. However, there are problems associated with depositing the ILD over the stacked interconnect structures.
When depositing the metal or metal alloy layers of the stacked interconnect structure or during subsequent thermal processing, in some instances metal alloys are newly formed at the interfaces of the individual layers. The newly formed metal alloys are constituted by the metals of the adjacent layers at a given interface. The formation of such newly formed metal alloys causes problems, especially when the newly formed metal alloy or alloys occupies less space or volume compared to the metals or metal alloys which make up the individual layers. When a newly formed metal alloy occupies less space (contraction in volume), voids are formed along the interconnect. The formation of metal voids is undesirable because they can lead to broken or inefficient lines and thus open, unreliable or faulty circuits.
For example, referring to FIG. 1A, in the case of a three layer stacked interconnect structure 12 made by depositing titanium nitride 12c over an aluminum alloy (e.g., Al with 1% Cu) 12b which in turn is deposited over a layer of titanium 12a, and patterning the metal stack into metal lines. Al and Ti at the aluminum alloy/titanium interface interact to form TiAl.sub.3 during deposition of the aluminum alloy or subsequent thermal processing. Since TiAl.sub.3 occupies less volume than either the aluminum alloy or titanium, it is believed that small voids 16 may be formed as indicated in the Ti/A1 alloy/TiN stacked interconnect structure 12. Nevertheless, due to cooling from the ILD deposition temperature, the metals and metal alloys of the stacked interconnect structure attempt to contract more than its surroundings permit, leading to the generation of large hydrostatic strains in the metal lines. The hydrostatic strains result in metal contraction. Consequently, referring to FIG. 1B, large voids 18 are formed at the Ti/Al alloy interface in the Ti/Al alloy/TiN stacked interconnect structure 12, especially at the sidewall of the metal lines where the temperature effects are most pronounced.
The occurrence of voids attributable to the formation of TiAl.sub.3 is typically unavoidable at 390.degree. C. or higher processing temperatures and the cooling effects of ILD deposition. In particular, deposition of the ILD promotes an increase in metal voiding (both an increase in size of existing voids in the metal and an increase in the number of metal voids), for example as shown in FIG. 1B (compared to FIG. 1A). Voiding is a particular problem in stacked interconnect structures containing at least one layer of aluminum or aluminum alloy. It is desirable to provide an integrated circuit having stacked interconnect structures with reduced metal voidings in order to prevent failures in electrical lines due to open circuits thus increasing reliability.